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Homework03

Due in Github Monday, December 12th at 11:59pm.


Complete the following exercises from DDCA:

1. DDCA 7.30

Exercise 7.30 Using a diagram similar to Figure 7.53, show the forwarding and stalls needed to execute the following instructions on the pipelined ARM processor.

ADD R0, R4, R9
SUB R0, R0, R2
LDR R1, [R0, #60]
AND R2, R1, R0

Figure 7.53:


2. DDCA 8.10 (Hint: look at the given solution for Exercise 8.9) You only need to do (a), (b), and (c) below.

Exercise 8.10 Repeat Exercise 8.9 for the following repeating sequence of lw addresses (given in hexadecimal) and cache configurations. The cache capacity is still 16 words. 

74 A0 78 38C AC 84 88 8C 7C 34 38 13C 388 18C 

(a) direct mapped cache, b = 1 word 
(b) fully associative cache, b = 2 words 
(c) two-way set associative cache, b = 2 words
(d) direct mapped cache, b = 4 words

For your reference, here is Exercise 8.9:

Exercise 8.9 A 16-word cache has the parameters given in Exercise 8.8. Consider the following repeating sequence of lw addresses (given in hexadecimal): 

40 44 48 4C 70 74 78 7C 80 84 88 8C 90 94 98 9C 0 4 8 C 10 14 18 1C 20 

Assuming least recently used (LRU) replacement for associative caches, determine the effective miss rate if the sequence is input to the following caches, ignoring startup effects (i.e., compulsory misses). 

(a) direct mapped cache, b = 1 word 
(b) fully associative cache, b = 1 word 
(c) two-way set associative cache, b = 1 word 
(d) direct mapped cache, b = 2 words


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