CS 315

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Lab 9

For this lab you are going add a simple direct mapped cache to your Pipelined MIPS implementation.

In your testbench you are going to count the number of memory accesses and the number of hits.

You need to do this for both instruction memory and data memory.

We built a simple 8 block direct mapped cache in class:

module cache_dm(input clk,
             input [31:0] addr,
             output hit);
 
    reg [26:0] tag[7:0];
    reg valid[7:0];
 
    wire [2:0] set;
    wire [26:0] addrtag;
 
    assign addrtag = addr[31:5];
    assign set = addr[4:2];
 
    assign hit = valid[set] & (tag[set] == addrtag);
 
    always @(posedge clk)
    begin
        valid[set] = 1;
        tag[set] = addrtag;
    end
endmodule

You need to add this to your Pipelined MIPS processor and to your testbench.

In addition to counting instruction memory references and hits you also need to instantiate another cache for data memory.  You should count the number of data memory accesses (read or write) and the number of hits.

You final output should be:

imem reqs: <count>
imem hits: <count>
dmem reqs: <count>
dmem hits: <count>

For the data memory, you need to know when there is a valid data memory access in the Mem stage.

Develop a test program with function calls and loops that show effective cache behavior.

Test your cache with the original memfile.dat.