For this project you need to implement a 2-way set associative cache similar to the direct-mapped cache we implemented for Lab 9.  Your cache does not need to actually hold data, you just need to simulate how effective the cache will be for a given reference stream.

Since we are just simulating, you can add your cache_sa module to your Pipelined MIPS implementation along with the cach_dm implementation.  This way you can compare the two caches side by side.

You cache should still only hold 8 words.  That means it will have 4 sets.

You should implement a used bit (U) that keeps track of the last "way" used in the cache.  You should use the U bit as well as the V bits to determine which "way" in a set you should replace.

You should be able demonstrate code in which the 2-way set associative cache works better than the direct mapped cache.

Your output should be: