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Project04

ARM Single-Cycle Implementation in Logisim

Due Tuesday, December 6th at 11:59pm. Interactive Grading on Wednesday December 7th.

NOTE: If you don't start early, you will not finish this project. It is worth 15% of your grade.

For this project you are going to implement a single-cycle implementation of a subset of the ARMv7 instruction set using digital logic in Logisim.

Your implementation should be able to execute the machine code versions of the following Project02 functions: fib_iter, fib_rec, and sum_array.

Your goal is to follow the single-cycle design in DDCA 7.3. However, you will likely have to modify this design to accommodate additional instructions used in the Project02 functions.

I will provide a Python script that can be used to convert ARM object code into a text file that can be read by the Logisim ROM (read only memory) component (see below).

You need to submit your Logisim design file to Github. You should also submit instructions for executing each one of the Project02 functions.

Note for sum_array you will need to pre-populate RAM with the numbers that make up the input array. You may have to modify your assembly code to assume the array starts at data memory address 0. You will assume your stack pointer starts at the high data memory address.

Extra Credit (1 point each)
  • Be creative in displaying the processor state at the top schematic level.
  • Replace all Logisim components with your own components built from AND, OR, and NOT gates.
  • Implement additional instructions to get find_str() working.
  • Implement a multicycle version of your ARM subset as described in DDCA 7.4.
  • Implement a pipelined version of your ARM subset as described in DDCA 7.5.
  • For the pipelined processor implement branch prediction as described in DDCA 7.7.3.
  • Implement a direct mapped cache and integrate it into your single-cycle processor. See DDCA 8.3.2.
  • Implement a fully associative cache and integrate it into your single-cycle processor. See DDCA 8.3.2.
  • Implement a multi-way set associative cache and integrate it into your single-cycle processor. See DDCA 8.3.2.

makerom.py

makerom.py

 

import sys

 

hexdigits =  ['0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f']

 

print "v2.0 raw"

 

for line in sys.stdin:

    tokens = line.split()

    if len(tokens) < 2:

        continue

    if len(tokens[1]) != 8:

        continue

    if tokens[1][0] not in hexdigits:

        continue

    print tokens[1]

 

Usage

 

On a Raspberry Pi

 

$ objdump -d file.o | python makerom.py > file_rom.txt





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