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Digital Logic Animation with Sequential Logic

Due Wednesday, November 13th at 11:59pm.

Please put all the deliverables into your CS 315 Project05 GitHub repository.

For this mini-Project you are going design a circuit in Digital that can animate images using the Digital Graphics RAM display. You will create a minimum of four 8x8 images, which will be loaded into a ROM device. Your circuit will read the images from the ROM and update the pixels in the graphics RAM. In order to drive the animation you will implement a 16-bit counter using a 16-bit register. Except where noted, you need to build all of the subcomponents yourself. We will learn how to use the ROM and Graphics RAM in class. Your final submission should be a Digital circuit, that when simulated, shows a unique animation in the graphics window. The animation should cycle indefinitely. Your image should be a minimum of 8x8 pixels, although you can make this larger if you want.

Here are the components you must implement:
  • A 16-bit Ripple Carry Adder
  • A 16-bit Register using SR latches, D latches, and D flip-flops
  • A 16-bit Counter
  • A Control Unit that uses the counter as input and drives the ROM and Graphics RAM
Components you can use from Digital:
  • Graphics RAM
  • ROM
You will need to figure out how to create each image and then load the image data into the ROM component. Then you need to figure out how to extract the ROM data to feed the Graphics RAM.

You need to design your own images to load into the ROM.

Turn in your working .dig file

Extra Credit (1 point each)
  • 24 hours early submission.
  • Build a Carry Lookahead Adder instead of a Ripple Carry Adder.